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Datasheet, V1.3, 06 Feb 2007
CCM-PFC
ICE1PCS01 ICE1PCS01G
Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)
Pow e r M a na ge m e nt & S upply
Never
stop
thinking.
CCM-PFC Revision History: Previous Version: V1.2 Page Subjects ( major changes since last revision ) Update package information 2007-02-06 Datasheet
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Edition 2007-02-06 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen
(c) Infineon Technologies AG 1999. All Rights Reserved.
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CCM-PFC
Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)
Product Highlights
* * * * * *
* * * * * * * * * * * * * * * *
ICE1PCS01 ICE1PCS01G
ICE1PCS01
PG-DIP-8
Wide Input Range Output Power Controllable by External Sense Resistor Programmable Operating Frequency Output Under-Voltage Detection Fast Output Dynamic Response during LoadJumps Pb-free lead plating; RoHS compliant
ICE1PCS01G
PG-DSO-8
Features
Ease of Use with Few External Components Supports Wide Range Average Current Control External Current and Voltage Loop Compensation for Greater User Flexibility Programmable Operating/Switching Frequency (50kHz - 250kHz) Max Duty Cycle of 95% (typ) at 125kHz Trimmed Internal Reference Voltage (5V+2%) VCC Under-Voltage Lockout Cycle by Cycle Peak Current Limiting Over-Voltage Protection Open Loop Detection Output Under-Voltage Detection Brown-Out Protection Enhanced Dynamic Response Unique Soft-Start to Limit Start Up Current Fulfills Class D Requirements of IEC 1000-3-2
Description
The ICE1PCS01/G is a 8-pin wide input range controller IC for active power factor correction converters. It is designed for converters in boost topology, and requires few external components. Its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the IC. The IC operates in the CCM with average current control, and in DCM only under light load condition. The switching frequency is programmable by the resistor at pin 4. Both compensations for the current and voltage loop are external to allow full user control. There are various protection features incorporated to ensure safe system operation conditions. Examples are peak current limitation, brown-out protection and output under voltage detection. The internal reference is trimmed (5V+2%) to ensure precise protection and control level. The device has an unique soft-start function which limits the start up current thus reducing the stress on the boost diode.
Typical Application
Auxiliary Supply
85 ... 265 VAC
VOUT
VCC
EMI-Filter
SWITCH PFC-Controller
ICE1PCS01/ ICE1PCS01G Protection Unit
GATE FREQ
PWM Logic Driver
Voltage Loop Compensation
VSENSE
Variable Oscillator Current Loop Compensation
ISENSE
Ramp Generator Nonlinear Gain
GND
VCOMP
ICOMP
Type ICE1PCS01 ICE1PCS01G
Version 1.2
Package PG-DIP-8 PG-DSO-8
3 06 Feb 2007
CCM-PFC ICE1PCS01/G
1 1.1 1.2 2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.7 3.8 3.8.1 3.8.2 3.9 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 5
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Representative Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Start-up (Soft-Start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Brown-Out Protection (BOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Soft Over Current Control (SOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Open Loop Protection / Input Under Voltage Protect (OLP) . . . . . . . . . . .9 Output Under Voltage Detection (OUV) . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Over-Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Nonlinear Gain Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Enhanced Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Version 1.2
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06 Feb 2007
CCM-PFC ICE1PCS01/G
Pin Configuration and Functionality
1
1.1
Pin 1 2 3 4 5 6 7 8
Pin Configuration and Functionality
Pin Configuration
Symbol GND ICOMP ISENSE FREQ VCOMP Function IC Ground Current Loop Compensation Current Sense Input Switching Frequency Setting Voltage Loop Compensation ICOMP (Current Loop Compensation) Low pass filter and compensation of the current control loop. The capacitor which is connected at this pin integrates the output current of OTA2 and averages the current sense signal. ISENSE (Current Sense Input) The ISENSE Pin senses the voltage drop at the external sense resistor (R1). This is the input signal for the average current regulation in the current loop. It is also fed to the peak current limitation block. During power up time, high inrush currents cause high voltage drop at R1, driving currents into pin 3 which could be beyond the absolute maximum ratings. Therefore a series resistor (R2) of around 220 is recommended in order to limit this current into the IC. FREQ (Frequency Setting) This pin allows the setting of the operating switching frequency by connecting a resistor to ground. The frequency range is from 50kHz to 250kHz. VSENSE (Voltage Sense/Feedback) The output bus voltage is sensed at this pin via a resistive divider. The reference voltage for this pin is 5V. VCOMP (Voltage Loop Compensation) This pin provides the compensation of the output voltage loop with a compensation network to ground (see Figure 2). This also gives the soft start function which controls an increasing AC input current during start-up. VCC (Power Supply) The VCC pin is the positive supply of the IC and should be connected to an external auxiliary supply. The operating range is between 10V and 21V. The turn-on threshold is at 11.2V and under voltage occurs at 10.2V. There is no internal clamp for a limitation of the power supply. GATE The GATE pin is the output of the internal driver stage, which has a capability of 1.5A source and sink current. Its gate drive voltage is clamped at 11.5V (typically).
VSENSE VOUT Sense (Feedback) Input VCC GATE IC Supply Voltage Gate Drive Output
Package PG-DIP-8 / PG-DSO-8
GND
1
8
GATE
ICOMP
2
7
VCC
ISENSE
3
6
VSENSE
FREQ
4
5
VCOMP
Figure 1
Pin Configuration (top view)
1.2
Pin Functionality
GND (Ground) The ground potential of the IC.
Version 1.2
5
06 Feb 2007
2
RFI Filter D2 ... D5 L1 D1 R3 Vout C2 R4 R1 auxiliary supply R2 R7 C1
Figure 2
GND VCC GATE
PWM Logic Gate Driver
R S
250ns
Version 1.2
R S
Vin 85 ... 265 VAC
ICE1PCS01/G
Variable Oscillator
FREQ
2.5V
OSC CLK
Representative Block diagram
Protection Block
UVLO VCC
OTA3
Toff min
R5
Peak Current Limit Ramp Generator
300ns
Over-current Comparator PWM Comparator
C1
undervoltage lockout Protection Logic
C4
1.5V Deglitcher Fault
C2
Representative Block diagram
6
Voltage Loop
0.73 V
0 -ve
2.5V
output uv protect
VSENSE
C3
Current Sense Opamp
ISENSE
-1.43x
0.8V open-loop protect
OP1
VCOMP
Current Loop
R6
+/-30uA, 42uS
OTA1
ICOMP
Nonlinear Gain
Current Loop Compensation
C4
5V
C5
OTA2
C3
1.1mS +/-50uA linear range
Soft Over Current Control Soft Start 4.75V
+ve 0 -ve
5.25V
4.0V
S2
4.0V
Fault
Representative Block diagram
CCM-PFC ICE1PCS01/G
06 Feb 2007
Fault
Window Detect
S1
CCM-PFC ICE1PCS01/G
3
3.1
Functional Description
General
Functional Description
The ICE1PCS01/G is a 8 pin control IC for power factor correction converters. It comes in both DIP and DSO packages and is suitable for wide range line input applications from 85 to 265 VAC. The IC supports converters in boost topology and it operates in continuous conduction mode (CCM) with average current control. The IC operates with a cascaded control; the inner current loop and the outer voltage loop. The inner current loop of the IC controls the sinusoidal profile for the average input current. It uses the dependency of the PWM duty cycle on the line input voltage to determine the corresponding input current. This means the average input current follows the input voltage as long as the device operates in CCM. Under light load condition, depending on the choke inductance, the system may enter into discontinuous conduction mode (DCM). In DCM, the average current waveform will be distorted but the resultant harmonics are still low enough to meet the Class D requirement of IEC 10003-2. The outer voltage loop controls the output bus voltage. Depending on the load condition, OTA1 establishes an appropriate voltage at VCOMP pin which controls the amplitude of the average input current. The IC is equipped with various protection features to ensure safe operating condition for both the system and device. Important protection features are namely Brown-out protection, Current Limitation and Output Under-voltage Protection.
If VCC drops below 10.2V, the IC is off. The IC will then be consuming typically 200A, whereas consuming 18mA during normal operation. The IC can be turned off and forced into standby mode by pulling down the voltage at pin 6 (VSENSE) to lower than 0.8V. The current consumption is reduced to 3mA in this mode.
3.3
Start-up (Soft-Start)
Figure 4 and 5 show the operation of OTA1 during startup. It sources a constant 10.8A into the compensation network at pin 5 (VCOMP). The voltage at this pin rises linearly and so does the amplitude of the input current. As soon as the output voltage VOUT reaches 80% of its rated level, the startup procedure is finished and the normal voltage control takes over. In normal operation, the IC operates with a higher maximum current at OTA1 and therefore with a higher voltage loop gain in order to improve the dynamic behavior of the device. .
VSENSE
( R4 x VOUT ) R3 + R4
Soft Start 4.0V
10.8uA during Soft Start OTA1
VCOMP
S1
5V C3 Open-Loop Protect (OLP) 0.8V
3.2
Power Supply
R6 C4 C5
An internal under voltage lockout (UVLO) block monitors the VCC power supply. As soon as it exceeds 11.2V and the voltage at pin 6 (VSENSE) is >0.8V, the IC begins operating its gate drive and performs its SoftStart as shown in Figure 3. .
VVSENSE > 0,8 V VCC 11.2 V 10.5 V VVSENSE < 0,8 V VVSENSE > 0,8 V
ICE1PCS01/G
Figure 4
Soft Start Circuit
Soft Start VOUT < 80% rated Normal Operation VOUT > 80% rated
av(IIN)
t IC's State
OFF Soft Normal start Operation Open loop/ Standby Normal Operation OFF
t
Figure 5 Soft Start with controlled current The advantage of this technique is a soft-start function with lower stress for the boost diode but without the risk of audible noise.
Figure 3
State of Operation respect to VCC
Version 1.2
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CCM-PFC ICE1PCS01/G
Functional Description 3.4 System Protection
POUT(rated) POUT(max)
The IC provides several protection features in order to ensure the PFC system in safe operating range. Depending on the input line voltage (VIN) and output bus voltage (VOUT), Figure 6 and 7 show the conditions when these protections are active.
VCC > VCCUVLO VIN (VAC)
VINMIN(1)
IC's State
Normal Operation
BOP
(BOP occurs at VISENSE = -0.6V Max)
VCCSOC
PCL
VISENSE
0 t
-0.6V -0.73V
-1.08V
IC's State
(1)
Normal Operation
BOP
IC OFF
Figure 8
BOP, SOC and PCL Protection as function of VISENSE
VINMIN where BOP activates depends on the output power
Figure 6
VIN Related Protection Features
105% 100% 50% 16%
t
The VIN threshold for BOP to occur is dependent on the voltage at ISENSE and thus the output power. The rated output power with a minimum VIN (VINMIN) is 0.6 P OUT ( rated ) = V INMIN x -----------------R1 2 Due to the internal parameter tolerance, the maximum power with VINMIN before BOP occurs is 0.73 P OUT ( max ) = V INMIN x -----------------R1 2 And the BOP takes over the normal operation under rated output power latest at an input voltage of R1 2 V BOPMAX = P OUT ( rated ) x -----------------0.73 3.4.2 Soft Over Current Control (SOC) The IC is designed not to support any output power that corresponds to a voltage lower than -0.73V at the ISENSE pin. A further increase in the inductor current, which results in a lower ISENSE voltage, will activate the Soft Over Current Control (SOC). This is a soft control as it does not directly switch off the gate drive like the PCL. It acts on the nonlinear gain block to result in a reduced PWM duty cycle. 3.4.3 Peak Current Limit (PCL) The IC provides a cycle by cycle peak current limitation (PCL). It is active when the voltage at pin 3 (ISENSE) reaches -1.08V. This voltage is amplified by OP1 by a factor of -1.43 and connected to comparator C2 with a reference voltage of 1.5V as shown in Figure 9. A deglitcher with 300ns after the comparator improves noise immunity to the activation of this protection.
VOUT VOUT,Rated
PCL / SOC OLP OVP OUV OLP
Figure 7
VOUT Related Protection Features
The following sections describe the functionality of these protection features. 3.4.1 Brown-Out Protection (BOP) Brown-out occurs when the input voltage VIN falls below the minimum input voltage of the design (i.e. 85V for universal input voltage range) and the VCC has not entered into the VCCUVLO level yet. For a system without BOP, the boost converter will increasingly draw a higher current from the mains at a given output power which may exceed the maximum design values of the input current. The ICE1PCS01/G limits internally the current drawn from the mains and therefore also limits the input power. The difference of input and output power will result in decreasing output voltage. If the condition prolongs, the decreasing VOUT will terminate in output under voltage condition (OUV, 50% of rated), and the IC will be shut down (See section 3.4.5). Figure 8 shows the occurrence of BOP in respect to the ISENSE voltage.
Version 1.2
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CCM-PFC ICE1PCS01/G
Functional Description
"Electrical Characteristic" section. The recommended operating frequency range is from 50kHz to 250kHz. As an example, a R5 of 33k at pin FREQ will set a switching frequency FSW of 133kHz typically.
Full-wave Rectifier
Current Limit 1.5V
C2
Deglitcher
300ns
ISENSE
R2 1.43x IINDUCTOR R1
OP1
Turn Off Driver
3.6
Average Current Control
3.6.1 Complete Current Loop The complete system current loop is shown in Figure 10.
From Full-wave Retifier L1 R7 D1 C2 R4 R3 Vout
ICE1PCS01/G
Figure 9 3.4.4
Peak Current Limit (PCL)
R2
Open Loop Protection / Input Under Voltage Protect (OLP) Whenever VSENSE voltage falls below 0.8V, or equivalently VOUT falls below 16% of its rated value, it indicates an open loop condition (i.e. VSENSE pin not connected) or an insufficient input voltage VIN for normal operation. In this case, most of the blocks within the IC will be shutdown. It is implemented using comparator C3 with a threshold of 0.8V as shown in the IC block diagram in Figure 2. 3.4.5 Output Under Voltage Detection (OUV) In the event of main interrupt or brown-out condition, the PFC system is not able to deliver the rated output power. This will cause the output voltage VOUT to drop below its rated value. The IC provides an output under voltage detection that checks if VOUT is falling below 50% of its rated value. Comparator C4 as shown in the device block diagram (Figure 2) senses the voltage at pin 6 (VSENSE) with a reference of 2.5V. If comparator C4 trips, the IC will be shut down as in OLP. The IC will be ready to restart if there is sufficient VIN to pull VOUT out of OLP. 3.4.6 Over-Voltage Protection (OVP) Whenever VOUT exceeds the rated value by 5%, the over-voltage protection OVP is active as shown in Figure 7. This is implemented by sensing the voltage at pin VSENSE with respect to a reference voltage of 5.25V. A VSENSE voltage higher than 5.25V will immediately reduce the output duty cycle, bypassing the normal voltage loop control. This results in a lower input power to reduce the output voltage VOUT.
R1
GATE ISENSE
Current Loop
voltage proportional to averaged Inductor current
Gate Driver
ICOMP
Current Loop Compensation OTA2 1.1mS +/-50uA (linear range) S2 4V Fault
PWM Comparator
C1
RQ S
PWM Logic Nonlinear Gain
Input From Voltage Loop
C3
ICE1PCS01/G
Figure 10
Complete System Current Loop
It consists of the current loop block which averages the voltage at pin ISENSE, resulted from the inductor current flowing across R1. The averaged waveform is compared with an internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator C1 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the inductor current. The following sections describe the functionality of each individual blocks. 3.6.2 Current Loop Compensation The compensation of the current loop is done at the ICOMP pin. This is the OTA2 output and a capacitor C3 has to be installed at this node to ground (see Figure 10). Under normal mode of operation, this pin gives a voltage which is proportional to the averaged inductor current. This pin is internally shorted to 5V in the event of IC shuts down when OLP and UVLO occur. 3.6.3 Pulse Width Modulation (PWM) The IC employs an average current control scheme in continuous conduction mode (CCM) to achieve the power factor correction.
3.5
Frequency Setting
The switching frequency of the PFC converter can be set with an external resistor R5 at FREQ pin. The pin voltage VFREQ is typically 2.5V. The corresponding capacitor for the oscillator is integrated in the device and the R5/frequency relationship is given at the
Version 1.2
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06 Feb 2007
CCM-PFC ICE1PCS01/G
Functional Description
Assuming the voltage loop is working and output voltage is kept constant, the off duty cycle DOFF for a CCM PFC system is given as V IN D OFF = ------------V OUT From the above equation, DOFF is proportional to VIN. The objective of the current loop is to regulate the average inductor current such that it is proportional to the off duty cycle DOFF, and thus to the input voltage VIN. Figure 11 shows the scheme to achieve the objective.
ramp profile
3.6.4 Nonlinear Gain Block The nonlinear gain block controls the amplitude of the regulated inductor current. The input of this block is the voltage at pin VCOMP. This block has been designed to support the wide input voltage range (85-265VAC).
3.7
PWM Logic
ave(IIN) at ICOMP
The PWM logic block prioritizes the control input signals and generates the final logic signal to turn on the driver stage. The speed of the logic gates in this block, together with the width of the reset pulse TOFFMIN, are designed to meet a maximum duty cycle DMAX of 95% at the GATE output under 133kHz of operation. In case of high input currents which result in Peak Current Limitation, the GATE will be turned off immediately and maintained in off state for the current PWM cycle. The signal Toffmin resets (highest priority, overriding other input signals) both the current limit latch and the PWM on latch as illustrated in Figure 13.
GATE drive
t
Figure 11 Average Current Control in CCM The PWM is performed by the intersection of a ramp signal with the averaged inductor current at pin 5 (ICOMP). The PWM cycle starts with the Gate turn off for a duration of TOFFMIN (250ns typ.) and the ramp is kept discharged. The ramp is then allowed to rise after TOFFMIN expires. The off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. This results in the proportional relationship between the average current and the off duty cycle DOFF. Figure 12 shows the timing diagrams of TOFFMIN and the PWM waveforms.
TOFFMIN 250ns PWM cycle
Peak Current Limit
Current Limit Latch Q S L1 R PWM on Latch S L2 R Q
G1
HIGH = turn GATE on
Current Loop PWM on signal Toffmin 250ns
Figure 13
PWM Logic
3.8
Voltage Loop
The voltage loop is the outer loop of the cascaded control scheme which controls the PFC output bus voltage VOUT. This loop is closed by the feedback sensing voltage at VSENSE which is a resistive divider tapping from VOUT. The pin VSENSE is the input of OTA1 which has an internal reference of 5V. Figure 14 shows the important blocks of this voltage loop. 3.8.1 Voltage Loop Compensation The compensation of the voltage loop is installed at the VCOMP pin (see Figure 14). This is the output of OTA1 and the compensation must be connected at this pin to ground. The compensation is also responsible for the soft start function which controls an increasing AC input current during start-up.
VCREF(1) VRAMP PWM ramp released
t
(1)
VCREF is a function of VICOMP
Figure 12
Ramp and PWM waveforms
Version 1.2
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06 Feb 2007
CCM-PFC ICE1PCS01/G
Functional Description
From Full-wave Retifier
L1 R7
D1 C2
R3
Vout
VCC
R4
PWM Logic HIGH to turn on
Gate Driver
LV Z1
External MOS
Current Loop + PWM Generation VIN
Nonlinear Gain
Gate Driver
GATE
GATE
* LV: Level Shift
Av(IIN)
OTA1
ICE1PCS01/G
5V
t
VSENSE
Figure 15
Gate Driver
ICE1PCS01/G
R6 C4
VCOMP
The output is active HIGH and at VCC voltages below the under voltage lockout threshold VCCUVLO, the gate drive is internally pull low to maintain the off state.
C5
Figure 14
Voltage Loop
3.8.2 Enhanced Dynamic Response Due to the low frequency bandwidth of the voltage loop, the dynamic response is slow and in the range of about several 10ms. This may cause additional stress to the bus capacitor and the switching transistor of the PFC in the event of heavy load changes. The IC provides therefore a "window detector" for the feedback voltage VVSENSE at pin 6 (VSENSE). Whenever VVSENSE exceeds the reference value (5V) by +5%, it will act on the nonlinear gain block which in turn affect the gate drive duty cycle directly. This change in duty cycle is bypassing the slow changing VCOMP voltage, thus results in a fast dynamic response of VOUT.
3.9
Output Gate Driver
The output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection and a Zener diode Z1 (see Figure 15) to protect the external transistor switch against undesirable over voltages. The maximum voltage at pin 8 (GATE) is typically clamped at 11.5V.
Version 1.2
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CCM-PFC ICE1PCS01/G
Electrical Characteristics
4
4.1
Note:
Electrical Characteristics
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit.
Parameter
VCC Supply Voltage FREQ Voltage ICOMP Voltage ISENSE Voltage ISENSE Current VSENSE Voltage VSENSE Current VCOMP Voltage GATE Voltage Junction Temperature Storage Temperature Thermal Resistance Junction-Ambient for DSO-8-3 Thermal Resistance Junction-Ambient for DIP-8-4 ESD Protection
1)
Symbol
VCC VFREQ VICOMP VISENSE IISENSE VVSENSE IVSENSE VVCOMP VGATE Tj TS RthJA (DSO) RthJA(DIP) VESD
Limit Values min.
-0.3 -0.3 -0.3 -24 -1 -0.3 -1 -0.3 -0.3 -40 -55 -
Unit
V V V V mA V mA V V C C K/W K/W kV
Remarks
max.
22 7 7 7 1 7 1 7 22 150 150 185 90 2
Recommended R2=220 R3>400k Clamped at 11.5V if driven internally.
PG-DSO-8-3 PG-DIP-8-4 Human Body Model1)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)
4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description.
Parameter
VCC Supply Voltage Junction Temperature
Symbol
VCC TJCon
Limit Values min.
-40
Unit
V C
Remarks
max.
125
VCCUVLO 21
Version 1.2
12
06 Feb 2007
CCM-PFC ICE1PCS01/G
Electrical Characteristics 4.3
Note:
Characteristics
The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from - 40 C to 125C.Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition.
4.3.1
Supply Section Symbol min.
VCCon VCCUVLO VCChy ICCstart ICCHG ICCStdby
Parameter
VCC Turn-On Threshold VCC Turn-Off Threshold/ Under Voltage Lock Out VCC Turn-On/Off Hysteresis Start Up Current Before VCCon Operating Current with active GATE Operating Current during Standby
Limit Values typ.
11.2 10.2 1 100 18 2.6
Unit Test Condition
V V V A mA mA VVCC=VVCCon -0.1V R5 = 33k CL= 4.7nF R5 = 33k VVSENSE= 0.5V
max.
11.9 10.8 1.3 200 22.5 3.2
10.5 9.4 0.8 50 13.5 2.0
4.3.2
Variable Frequency Section Symbol min.
FSWnom FSWmin FSWmax VFREQ
Parameter
Switching Frequency (Typical) Switching Frequency (Min.) Switching Frequency (Max.) Voltage at FREQ pin
Limit Values typ.
133 56 250 2.50
Unit Test Condition
kHz kHz kHz V R5 = 33k R5 = 82k R5 = 15k
max.
161 70 320 2.60
106 40 200 2.40
Version 1.2
13
06 Feb 2007
CCM-PFC ICE1PCS01/G
Electrical Characteristics
4.3.3 PWM Section Symbol min.
Max. Duty Cycle Min. Duty Cycle Min. Off Time DMAX DMIN TOFFMIN 150 250 92
Parameter
Limit Values typ.
95
Unit Test Condition
% % ns FSW = FSWnom (R5 = 33k) VVCOMP= 0V, VVSENSE= 5V VICOMP= 6.4V VVCOMP= 5V, VVSENSE= 5V VISENSE= 0.1V
max.
98 0 350
4.3.4
System Protection Section Symbol min.
VOLP VPCL VSOC VOUV VOVP
Parameter
Open Loop Protection (OLP) VSENSE Threshold Peak Current Limitation (PCL) ISENSE Threshold Soft Over Current Control (SOC) ISENSE Threshold Output Under Voltage Detection (OUV) VSENSE Threshold Output Over-Voltage Protection (OVP)
Limit Values typ.
0.81 -1.08 -0.73 2.55 5.25
Unit Test Condition
V V V V V
max.
0.86 -1.00 -0.66 2.65 5.38
0.77 -1.15 -0.79 2.45 5.12
Version 1.2
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06 Feb 2007
CCM-PFC ICE1PCS01/G
Electrical Characteristics
4.3.5 Current Loop Section Symbol min.
OTA2 Transconductance Gain OTA2 Output Linear Range ICOMP Voltage during OLP GmOTA2 IOTA2 VICOMPF 3.6 0.9
Parameter
Limit Values typ.
1.1 +/- 50 4.0
Unit Test Condition
mS A V At Temp = 25C Guaranteed by design VVSENSE= 0.5V
max.
1.3
4.3.6
Voltage Loop Section Symbol min.
VOTA1 GmOTA1 IOTA1SO IOTA1SK VSOFT IOTA1SS
Parameter
OTA1 Reference Voltage OTA1 Transconductance Gain OTA1 Max. Source Current Under Normal Operation OTA1 Max. Sink Current Under Normal Operation Soft Start End OTA1 Source Current Under Soft Start Enhanced Dynamic Response VSENSE High Threshold VSENSE Low Threshold VSENSE Input Bias Current at 5V VSENSE Input Bias Current at 1V VCOMP Voltage during OLP
Limit Values typ.
5.00 42 30 30 4.00 10.8
Unit Test Condition
V S A A V A VVSENSE= 2V VVCOMP= 0V VVSENSE= 4.25V VVCOMP= 4V VVSENSE= 6V VVCOMP= 4V
max.
5.10 52.5 38 38 4.20 13.4
4.90 31.5 21 21 3.80 8.0
VHi VLo IVSEN5V IVSEN1V VVCOMPF
5.12 4.63 0 0 0
5.25 4.75
5.38 4.87 1.5 1
V V A A V VVSENSE= 5V VVSENSE= 1V VVSENSE= 0.5V IVCOMP= 0.5mA
0.2
0.4
Version 1.2
15
06 Feb 2007
CCM-PFC ICE1PCS01/G
Electrical Characteristics
4.3.7 Driver Section Symbol
VGATEL -0.2 GATE High Voltage VGATEH GATE Rise Time GATE Fall Time GATE Current, Peak, Rising Edge GATE Current, Peak, Falling Edge
1)
Parameter
GATE Low Voltage
Limit Values min. typ.
0.8 1.6 0.2 11.5 10.5 7.5 20 20 1.5
Unit Test Condition
1.2 1.5 2.0 V V V V V V V V ns ns A A VCC = 5 V IGATE = 5 mA VCC = 5 V IGATE = 20 mA IGATE = 0 A IGATE = 20 mA IGATE = -20 mA VCC = 20V CL = 4.7nF VCC = 11V CL = 4.7nF VCC = VVCCoff + 0.2V CL = 4.7nF VGate = 2V ...9V CL = 4.7nF VGate = 9V ...2V CL = 4.7nF CL = 4.7nF1) CL = 4.7nF1)
max.
tr tf IGATE IGATE
-1.5 -
Design characteristics (not meant for production testing)
Version 1.2
16
06 Feb 2007
CCM-PFC ICE1PCS01/G
Outline Dimension
5
Outline Dimension
PG-DIP-8-4 (Plastic Dual In-Line Package)
Dimensions in mm
Figure 16 PG-DIP-8-4 Outline Dimension
PG-DSO-8-3 (Plastic Dual Small Outline)
1.75 MAX. 0.1 MIN. (1.5)
0.33 0.08 x 45 4 -0.21)
1.27 0.41 +0.1 -0.05 8 5
0.1
C
6 0.2
0.64 0.25
0.2 M A C x8
Index Marking 1
4
5 -0.21)
1)
A
Index Marking (Chamfer)
Dimensions in mm
Does not include plastic or metal protrusion of 0.15 max. per side
Figure 17 PG-DSO-8-3 Outline Dimension
Version 1.2
17
8 MAX.
0.2
+0.05 -0.01
06 Feb 2007
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